A NOVEL MEMORY CELL FOR MULTIPORT RAM ON 0.5-MU-M CMOS SEA-OF-GATES

A novel memory cell circuit for multiport RAM on CMOS Sea-of-Gates (SO G) has been proposed, It contributes to the operation both at high spe ed and at low voltage, In addition, a fourfold read bit Line technique is also proposed to reduce the access time. A multiport RAM generator with the novel memory cell has been developed. 2-port or 3-port RAM's with flexible bit-word configurations are available. Test chips conta ining seven generated RAM's were designed and fabricated on 0.5 mu m C MOS SOG, The experimental results of the chip show that each RAM opera tes at over 1.4 V and that the address access time of the 3-port RAM ( 16b x 256w) is 4.8 ns at 3.3 V.