TIMING AND AREA OPTIMIZATION FOR STANDARD-CELL VLSI CIRCUIT-DESIGN

A standard cell library typically contains several versions of any giv en gate type, each of which has a different gate size. We consider the problem of choosing optimal gate sizes from the library to minimize a cost function (such as total circuit area) while meeting the timing c onstraints imposed on the circuit. After presenting an efficient algor ithm for combinational circuits, me examine the problem of minimizing the area of a synchronous sequential circuit for a given clock period specification. This is done by appropriately selecting a size for each gate in the circuit from a standard-fell library, and by adjusting th e delays between the central clock distribution node and individual fl ip-flops. Experimental results show that by formulating gate size sele ction together with the clock skew optimization as a single optimizati on problem, it is not only possible to reduce the optimized circuit ar ea, but also to achieve faster clocking frequencies. Finally, we addre ss the problem of making this work applicable to very large synchronou s sequential circuits by partitioning these circuits to reduce the com putational complexity.