TIMING MODELS FOR GALLIUM-ARSENIDE DIRECT-COUPLED FET LOGIC-CIRCUITS

In this paper we derive delay and transition time macromodels for GaAs DCFL logic gates. The macromodels are derived by a systematic applica tion of dimensional analysis aimed at Ending suitable minimal function al forms that capture the effects of all relevant parameters. The proc ess is illustrated through a detailed step-by-step account of the macr omodel development for DCFL inverters. Based on different modeling app roximations, one- and two-argument macromodel functions are derived an d compared. The inverter macromodel is then used as a basis for develo ping timing macromodels for superbuffers and NOR gates. The NOR gate m acromodels account for the simultaneous and near-simultaneous switchin g of two inputs, with an extension to multiple inputs.