GEOMETRICAL FIGURE PROCESSING FOR IC LAYOUT EXTRACTED FROM SILICON DIE IMAGE

IC layouts can be extracted from silicon die images by using image pro cessing techniques. Due to the problem of an imperfect die surface and the limitations of the image processing, the extracted layouts can be distorted. To reconstruct the layouts, post-extraction processing is performed on the extracted layouts. This paper describes a set of tech niques developed to process the geometrical figures of extracted layou ts which aims to reconstruct the original layouts. The techniques incl ude not only basic geometrical figure processing, such as merging and expanding of figures, but also techniques specially developed for layo ut reconstruction, such as recovering the area of one layer beneath an other layer, extending figure edges with another figure on a different layer as a reference, etc. The paper presents the techniques and thei r application to the layout reconstruction. It also includes some exam ples and the processing results which show that the extracted layouts closely resemble originals after the post-extraction processing.