AUTOMATIC IMPLEMENTATION OF FIR FILTERS ON FIELD-PROGRAMMABLE GATE ARRAYS

This letter describes a CAD system for automatic implementation of FIR filters on Xilinx field programmable gate arrays (FPGA). Given the fr equency specifications, this software package designs an FIR filter, o ptimizes the filter coefficients in the power of two coefficient space , and implements it on FPGA chips. The FPGA specific mapping technique s used to increase speed are discussed. The performance of the typical filters that were implemented is presented.