VLSI ARCHITECTURES FOR THE DISCRETE WAVELET TRANSFORM

A class of VLSI architectures based on linear systolic arrays, for com puting the 1-D Discrete Wavelet Transform (DWT), is presented. The var ious architectures of this class differ only in the design of their ro uting networks, which could be systolic, semisystolic, or RAM-based. T hese architectures compute the Recursive Pyramid Algorithm, which is a reformulation of Mallat's pyramid algorithm for the DWT. The DWT is c omputed in real time (running DWT), using just N-omega(J-1) cells of s torage, where N-omega is the length of the filter and J is the number of octaves. They are ideally suited for single-chip implementation due to their practical I/O rate, small storage, and regularity. The N-poi nt 1-D DWT is computed in 2N cycles. The period can be reduced to N cy cles by using N-omega extra MAC's. Our architectures are shown to be o ptimal in both computation time and in area. A utilization of 100% is achieved for the linear array. Extensions of our architecture for comp uting the M-band DWT are discussed. Also, two architectures for comput ing the 2-D DWT (separable case) are discussed. One of these architect ures, based on a combination of systolic and parallel filters, compute s the N-2-point 2-D DWT, in real time, in N-2+N cycles, using 2NN(omeg a) cells of storage.