DESIGN OF 1.28-GB S HIGH-BANDWIDTH 2-MB SRAM FOR INTEGRATED MEMORY ARRAY PROCESSOR APPLICATIONS/

We have fabricated a high yield Integrated Memory Array Processor (IMA P) LSI, which features a high memory bandwidth (1,28-GB/s) and low pow er consumption (4-W max.) and which contains a 2-Mb SRAM with 128-I/O' s and 64 processor elements (PE's) in one chip, A high-bandwidth and l ow-power memory circuit design is the key technology to realize the IM AP/LSI, We adopted following new designs for memory circuit. 1) Memory access time is designed to be twice as fast as PE execution time 2) E mployment of dynamic power control mode, which reduces the memory powe r consumption down to 30% of maximum power without a loss in access-sp eed 3) Simplified synchronization with PE's 4) 4-way block redundancy. These design techniques are suitable for future system integrated ULS I's.