EXPERIMENTAL CHARACTERIZATION OF CIRCUITS FOR CONTROLLED PROGRAMMING OF FLOATING-GATE MOSFETS

This paper presents the results of measurements performed on test stru ctures implementing circuits for controlled erase of floating gate MOS FET's. The obtained results show that, with cells fabricated using sta ndard technology, the obtained performance is sufficiently good to all ow use in analog applications. The circuit has been demonstrated to be robust with respect to variations of the programming pulse characteri stics and to partially compensate cell aging effects on the threshold window. This latter feature is particularly interesting for digital ap plications because it allows the reduction of the window margin, thus improving memory endurance.