St. Chakradhar et al., ENERGY MODELS FOR DELAY TESTING, IEEE transactions on computer-aided design of integrated circuits and systems, 14(6), 1995, pp. 728-739
We present a new formulation of the delay testing problem as an energy
minimization problem, Two important applications have motivated this
work, First, it can be used to efficiently generate robust and nonrobu
st tests for path delay faults in scan and hold type of sequential cir
cuits, Second, it allows the design of a special class of delay fault
testable circuits, called (k, K)-circuits, that have polynomial-time t
est generation complexity, For the new formulation, the relationship b
etween input and output signal states of a logic gate for an arbitrary
pair of input vectors is expressed through an energy function, The mi
nimum-energy states of this function correspond to signal values that
are consistent with the gate's logic function, The function also impli
citly includes the information about the potential hazards due to arbi
trary delay distributions in the circuit, The energy function for the
circuit is the summation of the individual gate energy functions, To d
erive tests for a given delay fault, this function is suitably modifie
d such that any minimum-energy state is guaranteed to be a test, The s
pecific modifications to the energy function depend on the type (robus
t or nonrobust, with or without hazards) of delay test desired, For (k
, K)-circuits, we show that the energy function can be minimized in po
lynomial-time. For general circuits, where the problem still has an ex
ponential complexity, the recently proposed transitive closure based t
est generation technique is very effective in generating tests, This a
pproach efficiently determines a delay test or establishes that no tes
t is possible for the given delay fault, We report experimental result
s on various sequential benchmark circuits (full-scan versions) showin
g the feasibility and practicality of the new methods.