A new device concept, called the dual gate base resistance controlled
thyristor (DG-BRT), is introduced for simultaneously obtaining the low
on-state voltage drop of a thyristor together with a good forward bia
sed safe operating area. The two gates are used to control an N-channe
l and a P-channel MOSFET integrated with a thyristor structure using t
he DMOS process. When a positive bias is applied to both gates, the de
vice operates in the thyristor-mode dth a low on-state voltage drop at
even high current densities, When a negative bias is applied to the O
FF-gate, the device operates in the IGBT-mode, with the saturated curr
ent controlled by the positive bias applied to the ON-gate, The result
s of two-dimensional numerical simulations and measurements performed
on devices with 600 V forward blocking capability are reported.