AN EFFICIENT RESPONSE-SURFACE TECHNIQUE FOR INVESTIGATING CMOS PROCESS-RELATED EFFECTS ON CIRCUIT ELECTRICAL PERFORMANCE

The ability to simulate the effects of process technology on final pro duct circuits has become virtually indispensable in modern VLSI produc tion. It is especially significant as a tool for controlling parametri c yield by appropriate design centering and in determining the sensiti vity of the electrical parameters to process control tolerances. The s ystem demands the combined use of process simulation [1,2] device simu lation [3,4] and circuit simulation [5] all three of which rely heavil y on computationally intensive numerical solution of partial different ial equations. The severe computational overhead involved in 'technolo gy simulation TCAD)' means it is generally expensive and limits the sc ope of statistical design centering and optimisation, which depend on a large number of simulations. A compromise solution is often resorted to by limiting simulation to one or two spatial dimensions, replacing numerical simulation by analytical approximations as implemented in t he statistical process simulator: FABRICS 11[6], or combining numerica l and analytical models as in the process/device simulator PRIDE [7].) This paper addresses the problem of simpler, higher efficiency TCAD e valuation by restricting the domain of the simulation and approximatin g the process/device characteristic relationship by a set of simple, c omputationally efficient empirical equations. These equations offer a high speed solution at the expense of decreasing accuracy away from th e nominal process centre. Referred to as a 'response surface model', i t is generated using the results of a small number of statistically de signed TCAD simulations [8]. As the process sample is centred around t he nominal design parameters, the model can be used to statistically a nalyze the effects of process perturbations [9,10].