VLSI DESIGN AND IMPLEMENTATION OF SYSTOLIC TREE QUEUES

A number of innovative designs have been proposed for hardware impleme ntation of data structures. However, these designs have only been pres ented at an abstract behavioural level. in this paper, we describe the VLSI design and implementation of a 15-node 8-bit queue based on a sy stolic tree architecture. A layout methodology and a VLSI CAD environm ent that facilitate fast and efficient layout of large binary trees ar e described. The objective of this paper is to illustrate the implemen tation of tree architectures in VLSI. We demonstrate this by implement ing a systolic tree queue.