The gettering of Cu and Ni impurities in intentionally contaminated SI
MOX wafers have been studied by means of cross-sectional transmission
electron microscopy, nanoprobe energy dispersive x-ray spectroscopy, s
econdary ion mass spectrometry, and selective etching. The wafers with
Cu or Ni surface concentrations ranged from about 10(12) up to 10(17)
atom/cm(2) were annealed at various temperatures followed by slow coo
ling to room temperature. Single and multistep thermal treatments were
applied. It has been found that the buried oxide does not prevent the
diffusion of both Cu and Ni contaminants from the top silicon layer i
nto the bulk substrate at the whole investigated temperature range fro
m 600 to 950 degrees C. Moreover the effective gettering of Cu and Ni
in the thin silicon substrate layer located just beneath the buried ox
ide has been observed and explained as being due to the heterogeneous
impurity precipitation at stacking fault tetrahedra formed there durin
g the SIMOX manufacturing. The gettering process has remained stable d
uring the thermal simulation of CMOS device process of new generation
ICs with 0.25 mu m feature size.