LOGIC SYNTHESIS FOR RELIABILITY - AN EARLY START TO CONTROLLING ELECTROMIGRATION AND HOT-CARRIER EFFECTS

Designing reliable CMOS chips involves careful circuit design with att ention directed to some of the potential reliability problems such as electromigration and hot-carrier effects. This paper considers logic s ynthesis to optimize, early in the design phase, against electromigrat ion and hot-carrier degradation. The electromigration and hot-carrier effects are estimated at the gate level using signal activity measure (average number of transitions at circuit nodes). Results on MCNC synt hesis benchmarks show that logic can be synthesized to optimize for hi gher reliability and lower silicon area. A minimum-area circuit is usu ally not associated with highest reliability.