CIPHERING HARDWARE FOR HIGH-SPEED DIGITAL NETWORKS - A REDOC-III IMPLEMENTATION

Authors
NORAS JM
Citation
Jm. Noras, CIPHERING HARDWARE FOR HIGH-SPEED DIGITAL NETWORKS - A REDOC-III IMPLEMENTATION, Electronics Letters, 31(11), 1995, pp. 851-852
Citations number
3
Categorie Soggetti
Engineering, Eletrical & Electronic
Journal title
Electronics Letters → ACNP
ISSN journal
00135194
Volume
31
Issue
11
Year of publication
1995
Pages
851 - 852
Database
ISI
SICI code
0013-5194(1995)31:11<851:CHFHDN>2.0.ZU;2-0
Abstract
REDOC III, an algorithm for data ciphering with a predicted throughput in hardware of over 1Gbit/s, is a proposed replacement for DES. A Xil inx 4000 implementation, with simulation results that confirm the pote ntial system performances, is reported.