TRENDS OF SILICON-WAFER SPECIFICATIONS VS DESIGN RULES IN ULSI DEVICEFABRICATION - PARTICLES, FLATNESS AND IMPURITY DISTRIBUTION DEVIATIONS

Previously described empirical relations between the design rules and the past trends of the smallest size and number of particles, warpage, LTV(Local Thickness Variation), OSF(Oxidation-induced Stacking Fault density) and sheet resistance deviation capable of causing a scrapping die are discussed with theoretical considerations for DRAM(Dynamic Ra ndom Access Memory), gate array devices and microprocessor unit device s. Under the assumption that these trends will continue to the generat ion of the smallest design-rule transistor operating at room temperatu re, the target wafer specifications and future technical issues are pr edicted.