A DETERMINISTIC BUILT-IN SELF-TEST GENERATOR BASED ON CELLULAR-AUTOMATA STRUCTURES

This paper proposes a new approach for designing a cost-effective, on- chip, deterministic, built-in, self-test generator. Given a set of pre computed test vectors (obtained by an ATPG tool) with a predetermined fault coverage, a simple test vector generator (TVG) is synthesized to apply the given test set in a minimal test time. To achieve this obje ctive, cellular automata (CA) structures have been used in which the r ule space is not limited to the linear rules commonly used in CA studi es recently. Based on some new notations and new formulations of CA pr operties, two techniques are developed to synthesize such a TVG which is used to generate an ordered/unordered deterministic test vector set . The resulting TVG is very efficient in terms of hardware size and sp eed performance, and is very regular and testable. Simulation of vario us benchmark combinational circuits has given good results when compar ed to alternative solutions.