SINGLE-REFERENCE MULTIPLE INTERMEDIATE SIGNATURE (SREMIS) ANALYSIS FOR BIST

Compared to single signature analysis, checking multiple intermediate signatures has many advantages, e.g., smaller aliasing, easier computa tion of exact fault coverage, and shorter average test time. Conventio nally, checking n signatures requires n references. Storing these refe rences and comparing them with collected signatures imposes considerab le hardware requirements. In this paper, we propose a novel multiple i ntermediate signature analysis scheme which checks n signatures agains t a single reference, thus making the circuitry for checking n signatu res essentially the same as that for checking only one. The cost for i mplementing the proposed scheme is a very small nonrecurring CPU time expenditure in the design phase with no CUT modifications. In return, the proposed scheme yields significant recurring silicon area savings as well as reduced aliasing, and consequently higher test quality. Thi s paper also defines a property for linear compactors that guarantees the existence of an initial state that necessarily yields two identica l signatures at arbitrary check points for all circuits.