ON THE DESIGN OF A REAL-TIME VOLUME RENDERING ENGINE

An architecture for a Real-Time Volume Rendering Engine (RT-VRE) is gi ven, capable of computing 750 x 750 x 512 samples from a 3D dataset at a rate of 25 images per second. The RT-VRE uses for this purpose 64 d edicated rendering chips, cooperating with 16 RISC-processors. A plane interpolator circuit and a composition circuit, both capable to opera te at very high speeds, have been designed for a 1.6 micron VLSI proce ss. Both the interpolator and composition circuit are back from produc tion. They have been tested and both complied with our specifications.