500-V, N-CHANNEL ATOMIC LATTICE LAYOUT (ALL) IGBT WITH SUPERIOR LATCHING IMMUNITY

Authors
PARTHASARATHY V SO KC SHEN Z CHOW TP
Citation
V. Parthasarathy et al., 500-V, N-CHANNEL ATOMIC LATTICE LAYOUT (ALL) IGBT WITH SUPERIOR LATCHING IMMUNITY, IEEE electron device letters, 16(7), 1995, pp. 325-327
Citations number
11
Categorie Soggetti
Engineering, Eletrical & Electronic
Journal title
IEEE electron device letters → ACNP
ISSN journal
07413106
Volume
16
Issue
7
Year of publication
1995
Pages
325 - 327
Database
ISI
SICI code
0741-3106(1995)16:7<325:5NALL(>2.0.ZU;2-X
Abstract
Experimental and simulation results for the impact of Atomic Lattice L ayout (ALL) geometry on the latchup performance of 500 V n-channel IGB T's is reported here for the first time and is compared to the convent ional square, hexagonal and stripe geometries. It is shown that the AL L cell IGBT's provide a superior trade-off between optimization of for ward drop and latching current with a small penalty in the forward dro p.