Bulk synchronous parallel architecture incorporates a scalable and tra
nsparent communication model, The task-level synchronisation mechanism
of the machine, however, is not transparent to the user and can be in
efficient when applied to the co-ordination of irregular parallelism.
This article presents a discussion of an alternative memory-level sche
me which offers the prospect of achieving both efficient and transpare
nt synchronisation, The scheme, based on a discrete event simulation p
aradigm, supports sequential style of programming and, coupled with th
e BSP communication model, leads to the emergence of a virtual von Neu
mann parallel computer.