KEYNOTE PAPER - HARDWARE COMPILATION - A NEW TECHNIQUE FOR RAPID PROTOTYPING OF DIGITAL-SYSTEMS APPLIED TO SENSOR VALIDATION

This paper provides tutorial introductions to Field-Programmable Gate Arrays (FPGAs) and the concept of hardware compilation - the translati on of a high-level programming language directly into a hardware desig n. As an illustration, a simple stepper motor control program is prese nted. The research aims of the sensor validation programme are describ ed, and the benefits of using hardware compilation techniques are pres ented. This leads on in the conclusion of the paper to a more general discussion of the interaction between research and technology, and in particular the influence of information technology upon control engine ering.