AN ALL-DIGITAL PHASE-LOCKED LOOP WITH 50-CYCLE LOCK TIME SUITABLE FORHIGH-PERFORMANCE MICROPROCESSORS

A frequency-synthesizing, all-digital phase-locked loop (ADPLL) is ful ly integrated with a 0.5 mu m CMOS microprocessor, The ADPLL has a 50- cycle phase lock, has a gain mechanism independent of process, voltage , and temperature, and is immune to input jitter. A digitally-controll ed oscillator (DCO) forms the core of the ADPLL and operates from 50 t o 550 MHz, running at 4x the reference clock frequency, The DCO has 16 b of binarily weighted control and achieves LSB resolution under 500 fs.