AN ASYMPTOTICALLY ZERO POWER CHARGE-RECYCLING BUS ARCHITECTURE FOR BATTERY-OPERATED ULTRAHIGH DATA RATE ULSIS

An asymptotically zero power charge recycling bus (CRB) architecture, featuring virtual stacking of the individual bus-capacitance into a se ries configuration between supply voltage and ground, has been propose d, This CRB architecture makes it possible to reduce not only each bus -swing but also a total equivalent bus capacitance of the ultramultibi t buses running in parallel, The voltage swing of each bus is given by the recycled charge-supplying from the upper adjacent bus capacitance , instead of the power line. The dramatical power reduction was verifi ed by the simulated and measured data, According to these data, the ul trahigh data rate of 25.6 Gb/s can be achieved while maintaining the p ower dissipation to be less than 100 mW, which corresponds to less tha n 10% that of the previously reported 0.9 V suppressed bus-swing schem e, at V-cc = 3.6 V-or the bus width of 512 b with the bus-capacitance of 14 pF per bit operating at 50 MHz.