T. Ooishi et al., AN AUTOMATIC TEMPERATURE COMPENSATION OF INTERNAL SENSE GROUND FOR SUBQUARTER MICRON DRAMS, IEICE transactions on electronics, E78C(6), 1995, pp. 719-727
This paper describes DRAM array driving techniques and the parameter s
caling techniques for a low voltage operation using the boosted sense
ground (BSG) scheme and further improved methods, A temperature compen
sation and adjustable internal voltage levels maintain a small subthre
shold leakage current of a memory cell transistor (MC-Tr), and a distr
ibuted BSG (DBSG) scheme and a column decoded sensing (CDS) scheme ach
ieve the effective scaling, These schemes can set the DRAM array free
from a leakage current problem and free them from an influence of temp
erature variations. Therefore, parameters for the MC-Tr, threshold vol
tage (V-th), and the boosted voltage for the gate bias can be scaled d
own, and it is possible to determine the V-th of the MC-Tr easy (0.45
V at K = 0.4) for the satisfaction of the small leakage current, for t
he high speed and stable operation, and for the high reliability (V-pp
is below 2 V-cc), They are applicable to the subquarter micron DRAM's
of 256 Mb and more.