A 2.6-NS WAVE-PIPELINED CMOS SRAM WITH DUAL-SENSING-LATCH CIRCUITS

The dual-sensing-latch circuit proposed here can solve the synchroniza tion problem of the conventional wave-pipelined SRAM, and the proposed source-biased self-resetting circuit reduces both the cycle and acces s time of cache SRAM's. A 16-kb SRAM using these circuit techniques wa s designed, and was fabricated with 0.25-mu m CMOS technology, Simulat ion results indicate that this SRAM has a typical clock access time of 2.6 ns at 2.5-V supply voltage and a worst minimum cycle time of 2.6 ns.