A VLSI ARCHITECTURE FOR HIERARCHICAL MOTION ESTIMATION

Motion estimation is the critical path in compression algorithms, and several dedicated hardware solutions have been proposed for its accele ration. In this paper we present an innovative VLSI architecture for M otion Estimation that combines a low implementation cost with real-tim e performance for videoconferencing and DTV standards. To minimize com putational load and architecture requirements, we adopt a three-step h ierarchical search algorithm, that provides a quality comparable with more expensive full-search techniques. The proposed solution focuses o n architectural efficiency by employing a minimum set of functional un its (three simple processing units, one minimum unit, and four program mable delay lines), still supporting realtime performance for videocon ferencing standards. In addition we show how to combine parallel Motio n Estimation Units for backward-forward prediction (MPEG) and for high er throughput standards (DTV).