HIGH-RESOLUTION CMOS CURRENT COMPARATORS - DESIGN AND APPLICATIONS TOCURRENT-MODE FUNCTION GENERATION

This paper uses fundamental models to derive design conditions for max imum speed and resolution in CMOS transimpedance comparators. We disti nguish two basic comparator architectures depending on whether the inp ut sensing node is resistive or capacitive, and show that each type yi elds advantages for different ranges of input current. Then, we introd uce a class of current comparator structures which use nonlinear sensi ng and/or feedback to combine the advantages of capacitive-input and r esistive-input architectures. Two members of this class are presented demonstrating resolution levels (measured on silicon prototypes) in th e range of pAs. They exhibit complementary functional features: one, t he current steering comparator, displays better transient response in the very comparison function, while operation of the other, the curren t switch comparator, is easily extended to support systematic generati on of nonlinear transfer functions in current domain. The paper explor es also this latter extension, and presents current-mode circuit block s for systematic generation of nonlinear functions based on piecewise- linear (PWL) approximation. Proposals made in the paper are demonstrat ed via CMOS prototypes in two single-poly CMOS n-well technologies: 2 mu m and 1.6 mu m. These prototypes show measured input current compar ison range of 140 dB, resolution and offset below 10 pA, and operation speed two orders of magnitude better than that of conventional resist ive-input circuits. Also, measurements from the PWL prototypes show ex cellent rectification properties (down to a few pAs) and small lineari ty errors (down to 0.13%).