SYNTHESIS OF 2-PHASE QUASI-DELAY-INSENSITIVE CIRCUITS FROM DEPENDENCYGRAPHS

Recently, the efficiency of asynchronous circuits has again attracted a great deal of attention. In this paper, a synthesis method of delay- sensitive circuits is presented. In this method, a directed graph repr esenting dependencies between microoperations such as register transfe rs and arithmetic operations is given as the specification of a circui t. Under some constraints of the graph for correct synthesis, the cont rol circuit is implemented by translating graph nodes to the associate d circuit blocks. It controls data-paths in a two-phase manner by hand shakes. This method allows designers to describe parallelism easily in their specifications. The cost of synthesis is low.