T. Juhnke et H. Klar, CALCULATION OF THE SOFT ERROR RATE OF SUBMICRON CMOS LOGIC-CIRCUITS, IEEE journal of solid-state circuits, 30(7), 1995, pp. 830-834
A method to calculate the soft error rate (SER) of CMOS logic circuits
with dynamic pipeline registers is described, This methods takes into
account charge collection by drift and diffusion, The method is verif
ied by comparison of calculated SER's to measurement results, Using th
is method, the SER of a highly pipelined multiplier is calculated as a
function of supply voltage for a 0.6 mu m, 0.3 mu m, and 0.12 mu m te
chnology, respectively, It has been found that the SER of such highly
pipelined submicron CMOS circuits may become too high so that counterm
easures have to be taken, Since the SER greatly increases with decreas
ing supply voltage, low-power/low-voltage circuits may show more than
eight times the SER for half the normal supply voltage as compared to
conventional designs.