An integrated process for chemical vapor deposition (CVD) of titanium
(Ti) and titanium nitride (TiN) layers has been developed in which the
Ti process provides a uniform titanium silicide layer over silicon so
urce, drain, and gate regions, while the TiN process provides a confor
mal diffusion barrier over high-aspect-ratio features. Integrating the
CVD-Ti and CVD-TiN processes with an existing CVD-tungsten (W) proces
s provides a high-quality metallization module for devices with high-a
spect-ratio features at a low cost relative to collimated sputtering.
The integrated CVD process has been used to form sub-0.5-mu m test str
uctures as well as prime memories.