SURFACE-POTENTIAL DEPENDENCE OF INTERFACE STATE PASSIVATION IN METAL-TUNNEL OXIDE-SILICON DIODES

Interface state passivation during de biased post metallization anneal ing at similar to 350 degrees C was studied in very thin oxide, simila r to 31 Angstrom, aluminum-tunnel oxide-[111] p-type silicon structure s. Capacitance-voltage and tunnel current-voltage measurements were us ed after the anneals to monitor the passivation of interface states. I t was found that the passivation process of interface states in the as -manufactured devices is directly dependent on the surface potential b ut not on the average oxide electric held or the tunnel current. A neg ative gate voltage increases the passivation rate, whereas a positive gate voltage decreases it as compared to unbiased annealing. The inter face states resemble P-b centres, which are dangling bonds on trivalen tly bended Si atoms at the interface. The present observations are fou nd to agree well with theoretical calculations by Edwards (1991) on th e surface potential dependence of the passivation of P-b centers by H- 2. It is possible to find an optimum time and voltage for annealing, r oughly 1000 s and - 1.2 V in our case, for simultaneously minimizing t he de tunnel current, flatband voltage shifts and the density of fast interface states in these diodes.