A SIMULATED ANNEALING-BASED APPROACH TO 3-DIMENSIONAL COMPONENT PACKING

This paper introduces a simulated annealing-based approach to three-di mensional component packing that employs simulated annealing to genera te optimal solutions. Simulated annealing has been used extensively fo r two-dimensional layout of VLSI circuits; this research extends techn iques developed for two-dimensional layout optimization to three-dimen sional problems which are more representative of mechanical engineerin g applications. This research also provides a framework in which to so lve general component layout problems.