DOWNSIZING GOLD WIRES TO SUBMICRON RANGE - A SELF-PLANARIZED AU METALLIZATION PROCESS BY SELECTIVE ELECTROPLATING FOR SI LSI APPLICATIONS

A self-planarized Au metallisation process by electrolytic plating has been developed for metal interconnections in the submicron range. Gol d wires with depth-to-width aspect ratio higher than 2 were fabricated in a buried structure within the dielectric spacer. By etching of Au and oxidizing the surface of TiW in the field, the gold wires can be s electively formed and planarized within the dielectrics. This process can provide desired properties of conductor structures for Si LSI appl ications. More important, the process is economically viable due to it s simplicity and low cost in capital equipment purchase, maintenance a nd operation.