SEQUENTIAL HARDWARE PREFETCHING IN SHARED-MEMORY MULTIPROCESSORS

To offset the effect of read miss penalties on processor utilization i n shared-memory multiprocessors, several software- and hardware-based data prefetching schemes have been proposed, A major advantage of hard ware techniques is that they need no support from the programmer or co mpiler. Sequential prefetching is a simple hardware-controlled prefetc hing technique which relies on the automatic prefetch of consecutive b locks following the block that misses in the cache, thus exploiting sp atial locality. In its simplest form, the number of prefetched blocks: on each miss Is fixed throughout the execution, However, since the pr efetching efficiency varies during the execution of a program, we prop ose to adapt the number of prefetched blocks according to a dynamic me asure of prefetching effectiveness, Simulations of this adaptive schem e show reductions of the number of read misses, the read penalty, and of the execution time by up to 78%, 58%, and 25% respectively,