OPTIMIZED MULTIPLY ACCUMULATE ARCHITECTURE FOR VERY HIGH THROUGHOUT RATE DIGITAL-FILTERS/

Authors
MCGOVERN BP WOODS RF MCALLISTER C
Citation
Bp. Mcgovern et al., OPTIMIZED MULTIPLY ACCUMULATE ARCHITECTURE FOR VERY HIGH THROUGHOUT RATE DIGITAL-FILTERS/, Electronics Letters, 31(14), 1995, pp. 1135-1136
Citations number
4
Categorie Soggetti
Engineering, Eletrical & Electronic
Journal title
Electronics Letters → ACNP
ISSN journal
00135194
Volume
31
Issue
14
Year of publication
1995
Pages
1135 - 1136
Database
ISI
SICI code
0013-5194(1995)31:14<1135:OMAAFV>2.0.ZU;2-8
Abstract
A new modified circuit for implementing high performance IIR filters b ased on a pipelined multiply-accumulate (MAC) processor is proposed. C lever deployment of latches in the circuit allows the results to be ge nerated once every cycle thereby providing increased performance with reduced size and power consumption over previously designed circuits.