LAYOUT DRIVEN LOGIC SYNTHESIS SYSTEM

In a system level or logic level design process, the decisions made du ring early phases of the high level design have the greatest impacts o n the performance of the final chip. However, these impacts will not b e realised until very late in the physical design stage. In addition, it has been observed repeatedly that the most frustrating problem in I C design is to understand the relationship between the early phase dec isions and the final layout result. It is therefore important, in logi c synthesis to optimise a cost function which could relate the logic e quation and the final layout performance. The authors develop a logic synthesis approach which relies on an accurate design evaluation progr am to estimate the final design attributes such as layout area and spe ed. Given a candidate design implementation, an evaluation programme w ill be called upon to provide quick and accurate estimates of the layo ut area or critical path delay. This information will then be used as a feedback to the logic optimisation system, Based on this feedback, t he system will 'reorient' itself toward a new direction for optimisati on. Such a scheme represents a more realistic way of generating optima l layout implementations.