FUNCTIONAL TIMING ANALYSIS USING ATPG

Paths that are never exercised are referred to as false paths and timi ng analysis that ignores the delay contribution of these paths is refe rred to as functional timing analysis. Such timing analysis provides a more accurate estimate of circuit delay compared to conventional stat ic timing analysis. We show how unmodified conventional Automatic Test Pattern Generators (ATPG) for stuck at faults can be used for functio nal timing analysis without sacrificing computational efficiency in co mparison with existing approaches to the same problem. This is a signi ficant result since it enables us to use the entire body of work in AT PG for this problem and relieves us from re-inventing new solutions fo r this problem. The basic algorithm can be used under an arbitrary del ay model. We provide delay computation results for all the ISCAS bench mark examples under the unit-delay and the mapped-delay models.