TESTABLE DESIGN OF BICMOS CIRCUITS FOR STUCK-OPEN FAULT-DETECTION USING SINGLE PATTERNS

Single BJT BiCMOS devices exhibit sequential behavior under transistor stuck-OPEN (s-OPEN) faults. In addition to the sequential behavior, d elay faults are also present. Detection of s-OPEN faults exhibiting se quential behavior needs two-pattern or multipattern sequences, and del ay faults are all the more difficult to detect. A new design for testa bility scheme is presented that uses only two extra transistors to imp rove the circuit testability regardless of timing skews/delays, glitch es, or charge sharing among internal nodes, With this design, only a s ingle vector is required to test for a fault instead of the two-patter n or multipattern sequences. The testable design scheme presented also avoids the requirement of generating tests for delay faults.