A NEURON-MOS NEURAL-NETWORK USING SELF-LEARNING-COMPATIBLE SYNAPSE CIRCUITS

A circuit technology for self-learning neural network hardware has bee n developed using a high-functionality device called Neuron MOS Transi stor (nu MOS) as a key circuit element. A nu MOS can perform weighted summation of multiple input signals and thresholding all at a single t ransistor level based the charge sharing among multiple capacitors. An electronic synapse cell has been constructed with six transistors by merging a floating-gate EEPROM memory cell into a new-concept nu MOS d ifferential-source-follower circuitry. The synapse can represent both positive (excitatory) and negative (inhibitory) weights under single V -DD power supply and is free from standby power dissipation. An excell ent linearity in the weight updating characteristics of the synapse me mory has been also established by employing a simple self-feedback reg ime in each cell circuitry, thus making it fully compatible to the on- chip self-learning architecture of nu MOS neural networks. The basic o peration of the synapse cell and a nu MOS neural network using the syn apse has been experimentally verified using test circuits fabricated b y a double-polysilicon CMOS process.