FAST ADDERS USING ENHANCED MULTIPLE-OUTPUT DOMINO LOGIC

Using an enhanced multiple output domino logic (EMODL) implementation of a carry lookahead adder (CLA), sums of several consecutive bits can be built in one nFET tree with a single carry-in, Based on this resul t, a new sparse carry chain architecture is proposed for the CLA adder . We demonstrate the design approach using a 32-b adder, and show that only four carries are sufficient for generating all sums, with a cons equent reduction in the number of stage delays, Using a 1.2-mu m CMOS technology, we verify our simulation procedures by fabrication and mea surement of a 2.7 ns critical path.