A HIGH-SPEED, LOW-POWER BIPOLAR DIGITAL CIRCUIT FOR GB S LSIS - CURRENT MIRROR CONTROL LOGIC/

A novel low-power bipolar circuit for Gb/s LSI's, current mirror contr ol logic (CMCL), is described, To reduce supply voltage and currents, the current sources of emitter-coupled-logic (ECL) series gate circuit s are removed and the lower differential pairs are controlled by curre nt mirror circuits, This enables circuits with the same function as tw o-stacked ECL circuits to operate at supply voltage of -2.0 V and redu ces the current drawn through the driving circuits for the differentia l pairs to 50% of the conventional level shift circuits (emitter follo wers) in ECL, This CMCL circuit achieves 3.1-Gb/s (D-FF) and 43-GHz (T -FF) operation with a power supply voltage of -2.0 V and power dissipa tion of only 1.8 mW/(FF).