EVALUATION OF DESIGN PARAMETERS FOR LEADLESS CHIP RESISTORS SOLDER JOINTS

Failures in electronic packaging under thermal fatique often result fr om cracking in solder joints due to creep/fatigue crack growth. A nonl inear, time-dependent finite element analysis was performed to study t he effect of critical design parameters on thermal reliability of lead less chip capacitor or resistor solder joints. The shear strain range based on thermal hysteresis response was used to study the sensitivity of various parameters such as solder stand-off height, fillet geometr y, Cu-pad length, and component length and thickness. The results were used as guidelines for designing reliable solder joints. In addition, an analytical model for the solder joint assembly was derived. It can be used as an engineering approach for rapid assessment of large plum bers of design parameters. The accuracy and effectiveness of the analy tical model were evaluated by comparing with finite element results.