DEFECT AND FAULT-TOLERANT INTERCONNECTION STRATEGIES FOR WASP DEVICES

While WSI-based devices continue to be of particular interest for appl ications with severe performance, size, weight, power, cost, and relia bility requirements [1]-[3], various implementation constraints in the past, including interconnect defect occurrences, have prevented their successful realization, This paper presents an investigation into def ect and fault tolerant interconnect strategies for a representative WS I device, WASP (WSI Associative String Processor [3]).