INFLUENCE OF PROCESS PARAMETER VARIATIONS ON THE SIGNAL DISTRIBUTION BEHAVIOR OF WAFER-SCALE INTEGRATION DEVICES

With decreasing geometries of MOS transistors in VLSI devices, the inf luence of fluctuations of process parameters during manufacturing will become more and more important, because process tolerances are not pr oportionally scaled to geometries, These fluctuations result in a perf ormance spread of the devices produced by a certain process, For insta nce the clock rate of a microprocessor as a typical performance indica tor, can vary in a wide range. One of the key issues of the implementa tion of circuits using wafer scale integration technologies is the syn chronous distribution of signals, either clock, data or control over a large area of silicon, Fluctuations of process parameters can have a major influence on the performance of these devices. In the following paper, an efficient method for accurate prediction of the performance spread of integrated circuits will be discussed and demonstrated by si mulations, All the simulations will be verified by measurements on a t est-circuit on a huge number of test devices. The method will be appli ed to different signal distribution networks of wafer scale integratio n devices to show the sensitivity of performance to these variations.