A WAFER LEVEL TESTABILITY APPROACH BASED ON AN IMPROVED SCAN INSERTION TECHNIQUE

Testing strategies for complex WSI systems are one of the elements tha t may prevent the full exploitation of novel technologies, such as mul tichip modules (MCM's), because of the limited reliability (and qualit y) of the final product. The application of an efficient test strategy to the circuits of the module is necessary to achieve high-quality, c ost-effective devices, The aim of this paper is to introduce a structu red approach to the design of testable wafer scale devices, Bare die t estability is guaranteed through the application mainly of the Partial Scan methodology, to provide the most convenient solution in terms of overhead and performance, while module testability is achieved throug h the application of the Boundary Scan technique.