Baa. Antao et Aj. Brodersen, A FRAMEWORK FOR SYNTHESIS AND VERIFICATION OF ANALOG SYSTEMS, Analog integrated circuits and signal processing, 8(2), 1995, pp. 183-199
In this paper we present a framework for synthesis and verification of
analog systems. The famework is composed of a synthesis module and a
verification module. Synthesis is in the form of architectural synthes
is from behavioral specifications, and verification in the form of beh
avioral simulation of the synthesized architectures. The synthesis and
verification techniques are implemented in an object-oriented paradig
m, using an open systems approach which enables customizing the target
CAD framework. An Architecture Specification Language (ASL) is define
d using the C++ programming language constructs. The integrated synthe
sis-verification framework provides for design space exploration enabl
ing trade-offs in architectural as well as circuit technology characte
ristics. This paper focuses on the framework and implementation aspect
s of the architectural synthesis and verification methodology.