ANALOG 3-D NEUROPROCESSOR FOR FAST FRAME FOCAL-PLANE IMAGE-PROCESSING

A particularly challenging neural network application requiring high-s peed and intensive image processing capability is target acquisition a nd discrimination. It requires spatio-temporal recognition of point an d resolved targets at high speeds. A reconfigurable neural architectur e may discriminate targets forgets from clutter or classify targets on ce resolved. By mating a 64 x 64 pixel array infrared (IR) image senso r to a 3-D stack (cube) of 64 neural-net ICs along respective edges, e very pixel would directly input to a neural network, thereby processin g the infor-mation with full parallelism. Being mated to the infrared sensor array, the cube would operate at 90 degrees K temperature with <250 nanosecond signal processing speed and a low power consumption of only similar to 2 watts. For low power and compactness in hardware, t he emphasis has been on parallelism and analog signal processing. A ve rsatile reconfigurable circuit is presented that offers a variety of n eural architectures: multilayer perceptron, template matching with win ner-take-all (WTA) circuitry, and a new architecture of cascade backpr opagation (CBP). Special designs of analog neuron and synapse implemen ted in VLSI are presented which bear out high speed response both at r oom and low temperatures with synapse-neuron signal propagation times of similar to 100 ns. The CBP learning algorithm is illustrated by sol ving in simulation the nonlinear 6-bit parity problem. Results show th at this algorithm is robust even with synaptic resolutions limited to 5 bits. Therefore, it is particularly suitable for hardware implementa tion.