FULLY INTEGRATED CURRENT-MODE CMOS GATED BASE-LINE RESTORER CIRCUITS

Design and performance results for three different fully-integrated ga ted baseline restorer (BLR) circuits used in a new PET current-mode fr ont-end CMOS ASIC are presented. The BLR for each of the three gated i ntegrator channels is a differential current-in to single ended curren t-out circuit with a correction bandwidth of 100 kHz set by a 40 pF on -chip capacitor using pole splitting techniques. The BLRs for the cons tant fraction discriminator (CFD) constant fraction and arming compara tors are differential current-in to voltage-out circuits with correcti on bandwidths of 5 MHz and 1 MHz set by on-chip capacitors of 10 pF an d 2.5 pF respectively. The BLR circuits are capable of correcting diff erential input current offsets of +/- 40 mu A for the gated integrator circuits, +/- 100 mu A for the CFD constant fraction comparator circu it, and +/- 160 mu A for the CFD arming comparator circuit. Use of the BLR circuits allows photomultiplier tube (PMT) detector inputs to be ac coupled and all slow (gated integrator) and fast (CFD timing) signa l processing channels to be de coupled. The BLR circuits correct for c ount-rate dependent baseline shifts due to detector ac coupling and co rrect for accumulated CMOS de offsets in the signal processing channel s. Gated integrator input offset currents are maintained below 50 nA, keeping the gated integrator output error below 10 mV for an 850 ns in tegration period. CFD constant fraction comparator input offset is mai ntained at submillivolt levels, and arming comparator threshold is mai ntained at a 0-0.48 V level under on-board DAC control.