DESIGN AND PERFORMANCE OF AN ANALOG VLSI CELL FOR PIXEL DETECTOR READOUT - ANAPIX

An analogue VLSI cell for hybrid pixel detector readout, ANAPIX, has b een designed and tested. The chip has been manufactured in the FASELEC SACMOS 3 micron technology. A peak detector allows asynchronous signa ls to be processed without precise trigger timing. An equivalent noise charge of about 100 electrons r. m. s. has been achieved on tile cell alone. The cell has been wire bonded to a silicon detector pixel matr ix and in the laboratory energy spectra from radioactive gamma and bet a sources have been recorded with an equivalent noise charge of 200 el ectrons nns. The dynamic range design target of 500 to 50000 electrons was not achieved yet, due to a non linearity around 4000 electrons. T his problem is to be solved in the design of the second generation to be manufactured in a one micron technology. This new cell is to be con nected via bump bonding to a detector, the first assemblies are expect ed to be ready in 1995.